1. Field of the Invention
The present invention relates to an integrated circuit device incorporating a DLL (Delay Locked Loop) circuit and in particular relates to an integrated circuit device provided with a DLL circuit in which the accuracy of the phase regulation function of the DLL circuit is increased by reducing the effect of power source noise etc. applied through the power source from other circuits within the integrated circuit device.
2. Description of the Related Art
In synchronous integrated circuit devices such as synchronous DRAMs (SDRAMs), the internal circuitry is operated synchronously with a reference clock that is supplied from outside or with the timing of a prescribed phase relationship with the reference clock. For this purpose, they are provided internally with a timing clock generating circuit.
In such a timing clock generating circuit, a DLL circuit is employed in order to eliminate the effect of propagation delay of the reference clock in the integrated circuit device. Specifically, a DLL circuit comprises: a variable delay circuit that outputs a control clock having a prescribed timing by delaying the reference clock, and a phase comparison circuit and delay control circuit that compare the phases of the reference clock and the variable clock that is delayed therefrom, and regulate the amount of delay of the variable delay circuit such that these phases match. The basic layout of such a DLL circuit is shown for example in Laid-Open Japanese Patent Application No. H.10-112182 (laid open: Apr. 28, 1998).
FIG. 1 is a layout diagram of a prior art DLL circuit. In FIG. 1, there are shown a DLL circuit 1, an output circuit 2 and, as an example of a circuit other than a DLL circuit, an input buffer 3. The power source that is supplied to DLL circuit 1 is constituted by an internal power source Vii1 that is stepped down from an external power source. This stepped down internal power source Vii1 is generated by an internal power source system comprising a boosted power source generating circuit 4 that is supplied with external power Vcc and Vss and that generates boosted power Vpp by boosting up power vcc, a control, voltage (gate voltage) generating circuit 5 that generates a gate voltage Vg constituting a control voltage that is controlled to be constant and whose power is supplied by boosted power source Vpp, and an internal power source circuit VR1 that generates an internal power Vii1 that is lower by the amount of the threshold voltage of transistor Q1 from the gate voltage Vg.
In input buffer 3, there are provided input buffers 11, 10 that fetche clock CLK and its inverted clock /CLK into the interior from outside, and a dummy input buffer 18 that is utilized as part of the DLL circuit. Clocks /CLK0, CLK0 that are obtained from input buffers 10, 11 are respectively delayed by passing through variable delay circuits 12, 13 and are supplied to a data output buffer 14 as control clocks /CLK1, CLK1 controlled to prescribed phases. Data from inside, not shown, is output to the outside as output data Dout in response to these phase-controlled clocks /CLK1, CLK1. External power sources VccQ, VssQ for the external buffer, different from the ordinary external power sources Vcc and Vss are therefore supplied to this output buffer 14.
The feedback loop of the DLL circuit is supplied with a clock c-clk obtained by frequency division to a lower frequency by means of frequency divider 15 of internal clock CLK0. This reference clock c-clk is supplied as one input of phase comparison circuit 20. Whereas a variable clock d-i-clk after being delayed by variable delay circuit 16, dummy data output buffer 17, and dummy input buffer 18 is supplied to the other input of phase comparison circuit 20. The result of this phase comparison is supplied to phase control circuit 21, and phase control circuit 21 regulates the amount of delay of variable delay circuits 12, 13, 16 such that the phases of the two input clocks coincide. That is, a common delay control signal N21 is supplied to these variable delay circuits 12, 13, 16.
Apart from the above output buffer, the control clock is sometimes supplied to other prescribed internal circuitry so that the operating timings of this internal circuitry can be controlled. For example, the control clock may be supplied to an input buffer.
As described above, in the DLL circuit according to the prior art example, internal power source Vii1 for the DLL circuit is generated by an internal power source circuit VR1 exclusively for the DLL circuit 1, in order to avoid the effect of power source noise from the rest of the circuits. To circuits other than the DLL circuit 1, such as input buffer 3, external power source Vcc is supplied, or internal power source Vii2 from internal power source circuit VR2, which is different from internal power source circuit VR1 which is exclusively for the DLL circuit 1 is supplied. Also, to output circuit 2, which requires large current, external power sources VccQ, VssQ for the output circuit 2, which are different from the ordinary external power sources Vcc and Vss are supplied. Also, to DLL circuit 1, circuit 3 other than DLL circuit and power source systems 4, 5, externally earthed power source Vss is supplied.
However, the internal power source Vii1 that is stepped down in voltage and that drives the DLL circuit 1 is supplied to all the constituent elements of the DLL circuit 1. Consequently, power source noise is generated in internal power source Vii1 by the operation of each of the constituent elements of the DLL circuit. Thus, the power source noise generated by operation of some constituent elements of the DLL circuit affects the operation of other constituent elements. For example, when the inverted clock /CLK1 passes through the variable delay circuit 12, power source noise is produced in internal power source Vii1 by the operation of variable delay circuit 12 with the result that the amount of delay of other variable delay circuits 13, 16 that are driven by the same internal power source Vii1 fluctuates because of the effect of this power source noise. As a result, jitter (variation of phase) of the control clock is caused, making precise phase regulation difficult.
More specifically, when the reference clock c-clk and the variable clock d-i-clk passed through variable delay circuit 16 and dummy delay circuits 17, 18 go into the lock-on condition, power source noise is generated in internal power source Vii1 by the action of the other variable delay circuits 12, 13; this affects the operation of the variable delay circuit 16 in the feedback loop referred to above, causing its delay amount to change and in some cases may produce an unlocked condition. When this happens, even though the external clocks CLK, /CLK and control clocks CLK1, /CLK1 are in the lock-on condition, they are put into the unlocked condition by power source noise; this therefore results in jitter of the control clocks CLK1 and /CLK1, causing inaccurate timing of the output of data output Dout.
Also, as another example, phase comparison circuit 20 is provided with a phase coincidence detection unit for detecting whether or not the phase difference between the input clocks c-clk and d-i-clk is in the lock-on condition. In some cases, this phase coincidence detection unit, due to the effects of power source noise produced by the operation of variable delay circuits, detects the unlocked condition irrespective of the lock-on condition. In this case also, the delay control circuit 21 controls the amount of delay of variable delay circuit 16 in accordance with this phase comparison result and tries to achieve the lock-on condition, but at this point the effect of power source noise disappears so unlocking in respect of the variable clock d-i-clk after alteration of this delay amount is now detected, so delay control circuit 21 again controls the amount of delay of variable clock 6. Such phenomena cause jitter of the control clocks CLK1, /CLK1.
Furthermore, in the prior art example, external power sources Vcc and Vss are supplied to internal power source circuit VR1 which is exclusively for the DLL circuit 1; furthermore, the external ground power source Vss is also supplied to the control voltage (gate voltage) generating circuit 5 that generates a gate voltage Vg that is supplied to internal power source circuit VR1, and, moreover, external power sources Vcc and Vss are also supplied to boosted power source generating circuit 4 that generates boosted power source Vpp.
However, for example boosted power source generating circuit 4, with its pumping action of large current for generating the boosted power source, tends to generate power source noise in external power sources Vcc and Vss. Also, power source noise is generated in external power sources Vcc and Vss by the large current drive action of the word line or bit line that occurs on reading or writing of the memory circuit, not shown. Such power source noise produces fluctuation of the level of the gate voltage Vg generated by control voltage (gate voltage) generating circuit 5 for the DLL circuit and, furthermore, produces fluctuation of the level of the internal power source Vii1 generated by internal power source circuit VR1. As a result, due to the power source noise generated in internal power source Vii1, the amount of delay of the variable delay circuit within the DLL circuit fluctuates, thereby affecting the operation of the phase coincidence detection unit within the phase comparison circuit, causing jitter of the control clock, as mentioned above.
In future, when clock frequencies are made even higher, the effect of power source noise on the internal power source Vii1 from other constituent elements within the DLL circuit and/or the effect of power source noise on external power sources Vcc, Vss from circuits other than the DLL circuit will become impossible to ignore and the occurrence of clock jitter produced by these effects will have to be solved.
Accordingly, an object of the present invention is to provide an integrated circuit device having a DLL circuit in which jitter produced by power source noise is suppressed.
A further object of the present invention is to provide an integrated circuit device having a DLL circuit in which the effect of power source noise on the amount of delay of the variable delay circuit is suppressed.
A further object of the present invention is to provide an integrated circuit device having a DLL circuit in which the effect of power source noise on lock-on detection of the phase comparison circuit is suppressed.
A further object of the present invention is to provide an integrated circuit device in which the effect of power source noise on the internal power source system for the DLL circuit is suppressed.
Yet a further object of the present invention is to provide an integrated circuit device in which the effect of power source noise on the internal power source for the DLL circuit is suppressed.
In order to achieve the above objects, according to a first aspect of the invention, an external power source supplied to an integrated circuit device is divided into a first external power source for the DLL circuit and a second external power source for circuits other than the DLL circuit. The concept of xe2x80x9cexternal power sourcexe2x80x9d as referred to herein includes a ground power source (or earthing power source) and a power source different therefrom by a fixed voltage which are supplied from outside. Also, a power source different from the ground power source may be referred to simply as an external power source.
According to the present invention, it is arranged that power source noise generated in the second external power source cannot be transmitted to the variable delay circuit by utilizing the first external power source preferably for the variable delay circuit of the DLL circuit and even more preferably for its delay unit. Also, preferably, it is arranged that power source noise generated in the second external power source cannot be transmitted to the phase coincidence detection unit by utilizing the first power source for the phase coincidence detection unit (or simply comparison unit) in the phase comparison circuit of the DLL circuit. Also, by connecting the first external earthing power source to the variable delay circuit and/or phase coincidence detection unit, the effect of power source noise from the second external earthing power source originating from the operation of circuits other than these is suppressed.
According to the present invention, even more preferably, the internal power source system for the DLL circuit is divided into separate parts, namely, a part that supplies internal power source to the phase coincidence detection unit of the phase comparison circuit and/or the variable delay circuit in the DLL circuit, and a part that supplies internal power source to the constituent elements of the DLL circuit other than these. As a result, power source noise generated in the DLL circuit is arranged not to be transmitted to the internal power source of the phase coincidence detection unit and/or variable delay circuit, which are most critical to the accuracy of the phase regulation action of the DLL circuit. Furthermore, preferably, the internal power source circuits for the DLL that supply internal power source to the variable delay circuit or phase coincidence detection unit are separately constituted. As a result, mutual power source noise effects between the variable delay circuit and phase coincidence detection unit can be avoided.
Furthermore, according to the present invention, when an internal power source that is stepped down in voltage from the external power source is utilized in a circuit other than the DLL circuit, its internal power source circuit is provided independently of the internal power source circuit for the DLL for the phase coincidence detection unit and/or variable delay circuit of the DLL circuit. Furthermore, the control voltage generating circuit that supplies control voltage based on the internal power source to the internal power source circuit for the DLL is separately constituted from the control voltage generating circuit of the internal power source circuit for a circuit other than the DLL circuit. By suppressing the effect of power source noise on the control voltage (gate voltage), the operation of the DLL circuit can be made more precise.
Furthermore, according to the present invention, the external power source for output that is supplied to the integrated circuit device is divided into a first external power source for output for a dummy output buffer within the delay loop of the DLL circuit and a second external power source for output for the ordinary output buffer. By suppressing transmission of power source noise generated by the operation of the ordinary output buffer to the power source of the dummy output buffer of the DLL circuit that performs phase regulation of the clock, the amount of delay of the dummy output buffer is kept constant, making it possible to achieve stable phase regulation.
In order to achieve the above object, according to a second aspect of the invention, in order to suppress the effect of power source noise between the circuits constituting the DLL circuit, an internal power source circuit for the DLL is provided respectively independently for each of the plurality of variable delay circuits to which different clocks are supplied and pass therethrough.
Furthermore, according to the second aspect of the invention, preferably, the power sources of the delay unit, which is an item within the variable delay circuit that has comparatively little charging/discharging current is separated from the power source of the drive unit and output unit, which are items within the variable delay circuit that have comparatively large charging/discharging current. Thus, the delay unit is supplied with stepped-down internal power source from the internal power source circuit for the DLL. Further, although stepped-down internal power source is supplied to the drive unit, this drive unit is supplied with internal power source from an internal power source circuit for circuits other than the DLL circuit or internal power source circuit for the DLL independent of these circuits other than the DLL. If stepped down internal power source is supplied to the output unit, the internal power source supply is made in the same way as that of the drive unit. Also, external power source may be directly supplied to the output unit. In this case, preferably, a second external power source for a circuit other than the DLL circuit different from the first external power source for the DLL is supplied to the output unit. However, since the drive current amount of the voltage level conversion unit within the output unit is small and its power source noise is small, preferably it is supplied with first external power source.
Furthermore according to the second aspect of the invention, preferably, the power source of the delay element of the phase coincidence detection unit of the phase comparison circuit and the power source of items other than this are made separate. An internal power source that is stepped down from the internal power source for the DLL is supplied to the delay element of the phase coincidence detection unit. When stepped-down internal power source is supplied also to the circuits other than this, internal power source from the internal power source circuit for the circuits other than the DLL circuit or internal power source circuit for the DLL circuit that is separated from the internal power source circuit for the DLL circuit for the phase detection unit is supplied. Alternatively, external power source may be directly supplied to circuits other than the phase coincidence detection unit. In this case, preferably, a second external power source is supplied.
Thus, according to the second aspect of the invention, the delay unit of the variable delay circuit or the phase coincidence detection unit of the phase comparison circuit are supplied with internal power source from an internal power source circuit for the DLL that generates internal power source stepped down from the first external power source, and respective delay units or the phase coincidence detection unit are supplied with internal power source from respectively separate internal power source circuits for the DLL. As a result, the effect of power source noise on these delay characteristics can be suppressed.
Further, in order to achieve the above object, according to a third aspect of the invention, in an internal power source circuit for the DLL that supplies internal power source voltage stepped down from external voltage to the delay units of the variable delay circuit or the phase coincidence detection unit of the phase comparison circuit, the internal power source voltage is stabilized. With this purpose in view, it is arranged for a first external power source for the DLL to be supplied to the internal power source circuit for this DLL, so that noise from the second external power source is not transmitted. Further, the current supply capability of the internal power source circuit for this DLL is made to be approximately proportional to the power consumption of the respectively corresponding delay unit and/or phase coincidence detection unit. As a result, each internal power source circuit for the DLL can supply internal power source voltages having practically the same potential to each corresponding circuit.
Furthermore, according to the third aspect of the invention, in order to stabilize the control voltage (gate voltage) that is supplied to each internal power source circuit, a low-pass filter is inserted between the control voltage generating circuit and internal power source circuit, so as to cut off noise from the control voltage generating circuit. Furthermore, according to the third aspect of the invention, the internal power source circuit comprises a source follower type transistor whose drain is connected to a first external power source, whose gate is supplied with control voltage and whose source outputs internal power source; and a current circuit that extracts a prescribed current from the transistor provided between the source of this transistor and the earthing power source. More preferably, the amount of current that this current circuit extracts is dynamically controlled such that it is small in power-down mode but is larger in non-power-down mode. As a result, even if the delay units of the variable delay circuit and/or phase coincidence detection unit of the phase comparison circuit that are supplied with the internal power source do not consume current during power-down mode, a prescribed amount of current is absorbed by the current circuit, so the voltage of the source of the transistor can be prevented from rising excessively. Furthermore, in active mode, since the current circuit absorbs more current, even if current is consumed intermittently corresponding to the phase of the clock that is supplied by the variable delay units and/or phase coincidence detection unit, excessive rising or falling of the voltage of the source of the transistor can be prevented.
Furthermore, according to the third aspect of the invention, in order to stabilize the control voltage (gate voltage) of the control voltage (gate voltage) generating circuit that supplies control voltage to the internal power source circuit for the DLL, for the earthing power source of the control voltage generating circuit, the earthing power source of the first external power source is utilized. Furthermore, preferably, the control voltage generating circuit comprises an operational amplifier and a circuit construction whereby negative feedback of its output is effected to one input, the earthing power source wiring of the first external power source being arranged in parallel in the vicinity of a resistive element in the negative feedback circuit. The effect of power source noise to the resistive element can be suppressed by the shielding function of the earthing power source wiring of the first external power source, which is little affected by power source noise. Further, according to the third aspect of the invention, gate voltage from a common control voltage generating circuit is supplied to a plurality of internal power source circuits for the DLL. As a result, internal power sources of the same potential can be generated for the plurality of internal power source circuits for the DLL.
In order to achieve the above object, according to a fourth aspect of the invention, a second external power source is supplied to a boosted power source generating circuit that supplies a boosted power source to a control voltage generating circuit for the DLL. Since such a boosted power source generating circuit for the DLL generates boosted power source by a pumping action using the external power source, considerable power source noise is generated in this external power source. Consequently, according to the fourth aspect of the invention, by supplying a second external power source to the boosted power source generating circuit for this DLL, it is arranged that this power source noise is not transmitted to the first external power source.
According to the fourth aspect of the invention, preferably, the boosting action of the boosted power source generating circuit for the DLL is made slower than that of the boosted power source generating circuit for items other than the DLL. Alternatively, the amount of charge utilized in a single voltage boosting cycle in the boosted power source generating circuit for the DLL is made smaller. Furthermore, by inserting a resistance etc. in the boosted power source generating circuit for the DLL, the fluctuation of potential of the boosted power source produced by this pumping action is minimized. Also, preferably, a low-pass filter is inserted between the boosted power source generating circuit for the DLL and the control voltage generating circuit for the DLL. As a result, fluctuation of potential of the boosted power source produced by the pumping action of the boosted power source generating circuit can be prevented from being transmitted to the control voltage generating circuit.
As described above, according to the fourth aspect of the invention, it is possible to prevent power source noise generated by the boosted power source generating circuit or fluctuation of the boosted power source being transmitted to the control voltage generating circuit or internal power source circuit for the DLL.
In order to achieve the above object, according to a fifth aspect of the invention, a back bias power source that supplies the channel region of a transistor of a delay unit of the variable delay circuit or the phase coincidence detection unit of the phase comparison circuit is made separate from the back bias power source for the transistor of another circuit. By supplying the transistors of the delay units or phase coincidence detection unit with a dedicated back bias power source wherein the effect of noise generated on the back bias power source terminal of the other circuit is small, the threshold values of these transistors can be stabilized, making it possible to raise the precision of the delay time of the delay units and/or the delay time of the phase coincidence detection unit.
According to the fifth aspect of the invention, even more preferably, back bias power source of little noise likewise isolated from the back bias power source of the other circuit is supplied also to the transistors of the internal power source circuit for the DLL and of the control voltage generating circuit for the DLL that supplies control voltage thereto. As a result, the threshold voltage of the transistor that determines the control voltage is stabilized, thereby stabilizing the control voltage. Furthermore, the threshold voltage of the transistor of the internal power source circuit is stabilized, thereby stabilizing the potential of the internal power source.
Preferably, according to the fifth aspect of the invention, a prescribed capacitor is inserted between the isolated back bias voltage and the voltage of the cell plate of a memory cell, thereby further stabilizing the voltage value of the isolated back bias voltage.
In accordance with the objects, according to a sixth aspect of the invention, a control clock whose phase is regulated by the DLL circuit is supplied to a plurality of internal circuits through wirings of equal length, and a buffer circuit that drives the control clock is inserted at the branch points of these wirings of equal length. By arranging the drive buffer on wirings of equal length, the waveform of the control clock that is propagated thereon can be made steep, thereby enabling the effect of power source noise to be minimized.
Further, according to the sixth aspect of the invention, drive buffers equal in number thereto are connected at branch points corresponding to the plurality of wirings of equal length, the same stray capacitance is provided in respect of the wirings of equal length which have few branch leads, thereby equalizing the propagation speed of the control clock of these respective wirings of equal length. Also, the buffer circuits provided at corresponding branch points have respectively the same drive capability. Also, according to the sixth aspect of the invention;, the voltage wirings that supply back bias voltage of the transistors constituting the drive gate circuits are isolated from the wirings of the back bias voltage for the other circuits, thereby making it possible to avoid the operating speed of the drive buffer circuits being affected by the operation of other circuits. In addition, according to the sixth aspect of the invention, wiring of the first power source for the DLL is arranged parallel to the equal-length wiring, and preferably the equal-length wiring is shielded from other signal lines, such that the equal-length wiring is not affected by noise of other signal lines. In this way, the propagation speed of the control clock can be made to be approximately the same between a plurality of equal-length wirings.